Semiconductor devices such as system LSIs, semiconductor memory devices, etc., have a cell region where semiconductor elements are arranged in an array configuration, and a peripheral circuit that controls the semiconductor elements in the cell region from a peripheral region. Downscaling of the semiconductor elements and multilayering of the interconnect structure are progressing to increase an integration degree of the semiconductor device. For example, such a semiconductor memory device has a memory cell region including the semiconductor memory elements, a peripheral circuit region including a circuit at the periphery of the memory cell region to control the semiconductor memory elements in the memory cell region, and a multilayered interconnect structure at the upper portions of the memory cell region and the peripheral circuit region. Each of the interconnect layers of the multilayered interconnect structure includes interconnects (hereinbelow, called cell region interconnects) that are drawn out from the elements inside the memory cell region and interconnects (hereinbelow, called peripheral region interconnects) that are drawn out from the peripheral circuit in the peripheral circuit region. Downscaling progresses for the semiconductor memory element and the cell region interconnect as the memory capacity of the semiconductor memory device is increased. As a result, the electric resistance of the cell region interconnect increases; and the delay of control signals inside the memory cell region and the increase of heat generation may occur due to the increased interconnect resistance. Although there is a method in which a metal having a short mean free path is used to suppress the increase of the resistance of the cell region interconnect, the increase of the resistance of the peripheral region interconnect is problematic.